The invention relates to semiconductor devices and the fabrication thereof, and more particularly to semiconductor devices and the fabrication thereof for ultra-thin SOI semiconductor devices.
In the design of some semiconductor devices on silicon on insulator (SOI) wafers, and in particular on ultra thin SOI wafers, extension resistance can significantly limit the drive current. The extensions are the region of the semiconductor device which lead to the channel under the gate and generally provide external contact to a portion of the active region of the device.
Methods to reduce extension resistance include raising the source/drain region to reduce the extension resistance. Thus, the volume of conductive material leading away from the channel of the device is increased as well as providing an opportunity to form the raised source/drain regions from a material having a higher conductivity than the source/drain region.
In order to minimize the extension resistance by raising the source/drain region, the raised source/drain region should be arranged to lie close to the edge of the gate. However, if the raised source/drain region is too close to the gate edge, a parasitic capacitance known as gate overlap capacitance can increase significantly. Such gate overlap capacitance may negate any advantages of the raised source/drain region by increasing the total capacitance of the gate thereby curtailing the frequency response of the device.
Embodiments of the invention are directed to solving some or all of the problems discussed above.